;Data TLB1: 4 MByte pages, 4-way set associative, 32 entriesO1st level instruction cache: 8 KBytes, 4-way set associative, 32 byte line sizeP1st level instruction cache: 16 KBytes, 4-way set associative, 32 byte line sizeH1st level data cache: 8 KBytes, 2-way set associative, 32 byte line size@Instruction TLB: 4 MByte pages, 4-way set associative, 4 entriesI1st level data cache: 16 KBytes, 4-way set associative, 32 byte line sizeY3rd level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sectorW3rd level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sectorW3rd level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sectorW3rd level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sectorI1st level data cache: 32 KBytes, 8-way set associative, 64 byte line sizeP1st level instruction cache: 32 KBytes, 8-way set associative, 64 byte line sizeXNo 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cacheE2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line sizeE2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line sizeE2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size